The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2014
Filed:
Jan. 17, 2014
Applicants:
Yoshimitsu Yanagawa, Tokyo, JP;
Tomonori Sekiguchi, Tokyo, JP;
Akira Kotabe, Tokyo, JP;
Takamasa Suzuki, Tokyo, JP;
Inventors:
Yoshimitsu Yanagawa, Tokyo, JP;
Tomonori Sekiguchi, Tokyo, JP;
Akira Kotabe, Tokyo, JP;
Takamasa Suzuki, Tokyo, JP;
Assignee:
PS4 Luxco S.A.R.L., Luxembourg, LU;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03L 7/081 (2006.01); H03K 5/159 (2006.01); H03K 5/13 (2014.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/00 (2013.01); H03L 7/0816 (2013.01); H03K 2005/00032 (2013.01); H03K 5/159 (2013.01); H03K 5/133 (2013.01); H03K 2005/00052 (2013.01);
Abstract
Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.