The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

Nov. 05, 2012
Applicant:

Altera Corporation, San Jose, CA (US);

Inventor:

David Cashman, Toronto, CA;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
Abstract

Integrated circuits with repairable logic regions are provided. Each logic region may be organized into a predetermined number of rows of logic circuitry, one of which serves as a spare row. A repairable region may be operable in normal mode or redundant mode. In normal mode, the spare row is deactivated. When one of the logic region rows contains defective circuitry, that logic region is operated in redundant mode so that each row below the bad row is shifted down by one row and the spare row is engaged to serve as the last row to repair that region. Each row may include a multiplexer and an associated driver that drives a corresponding vertical routing segment from one row to the next. Each vertical routing segment has the option of being driven by its logically equivalent vertical wire in the immediate preceding row by configuring the corresponding multiplexer.


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