The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

Jan. 03, 2012
Applicants:

Joo-yang Eom, Bucheon, KR;

Joon-seo Son, Seoul, KR;

Inventors:

Joo-yang Eom, Bucheon, KR;

Joon-seo Son, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/20 (2006.01); H01L 23/433 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01); H01L 23/373 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3735 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/45014 (2013.01); H01L 2924/13091 (2013.01); H01L 21/56 (2013.01); H01L 23/4334 (2013.01); H01L 23/562 (2013.01); H01L 24/73 (2013.01); H01L 23/49811 (2013.01); H01L 2224/40247 (2013.01); H01L 2224/73221 (2013.01); H01L 2924/13055 (2013.01); H01L 24/34 (2013.01); H01L 23/3121 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/40137 (2013.01); H01L 25/0655 (2013.01);
Abstract

A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.


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