The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

Jul. 26, 2011
Applicants:

Kenji Shimada, Tokyo, JP;

Hiroshi Matsunaga, Tokyo, JP;

Kojiro Abe, Chiba, JP;

Kenji Yamada, Tokyo, JP;

Inventors:

Kenji Shimada, Tokyo, JP;

Hiroshi Matsunaga, Tokyo, JP;

Kojiro Abe, Chiba, JP;

Kenji Yamada, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 21/28 (2006.01); C09K 13/08 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 29/40 (2006.01); H01L 21/3213 (2006.01); C09K 13/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/401 (2013.01); C09K 13/08 (2013.01); H01L 21/823842 (2013.01); H01L 21/02068 (2013.01); H01L 21/82345 (2013.01); H01L 29/66545 (2013.01); H01L 21/31111 (2013.01); H01L 21/28079 (2013.01); H01L 21/32134 (2013.01); C09K 13/06 (2013.01);
Abstract

According to the present invention, there is provided a process for producing a transistor having a high precision and a high quality with a high yield by selectively etching a natural silicon oxide film, and further by selectively etching a dummy gate made of silicon. The present invention relates to a process for producing a transistor using a structural body which includes a substrate, and a dummy gate laminate formed by laminating at least a high dielectric material film and a dummy gate made of silicon having a natural silicon oxide film on a surface thereof, a side wall disposed to cover a side surface of the laminate and an interlayer insulating film disposed to cover the side wall which are provided on the substrate, said process including an etching step using a specific etching solution and thereby replacing the dummy gate with an aluminum metal gate.


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