The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

Jul. 31, 2009
Applicants:

John M. Bedinger, Garland, TX (US);

Michael A. Moore, Fort Worth, TX (US);

Inventors:

John M. Bedinger, Garland, TX (US);

Michael A. Moore, Fort Worth, TX (US);

Assignee:

Raytheon Company, Waltham, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01); H05K 3/28 (2006.01); H01L 23/482 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H05K 3/284 (2013.01); H01L 2224/73265 (2013.01); H05K 2201/0179 (2013.01); H01L 2924/1423 (2013.01); H05K 2203/1322 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/01004 (2013.01); H01L 23/4821 (2013.01); H01L 2924/01019 (2013.01); H01L 24/83 (2013.01); H01L 23/3192 (2013.01); H01L 2224/83801 (2013.01); H01L 2224/83851 (2013.01); H01L 2924/0781 (2013.01); H05K 2201/0195 (2013.01); H01L 2224/8592 (2013.01);
Abstract

A method includes providing a circuit board having an outer surface, the outer surface configured with a plurality of discrete electrical components that are each manufactured independently of one another, and coating the outer surface and the plurality of discrete electrical components with a first protective dielectric layer. The method further includes coating the first protective dielectric layer with a second dielectric layer. The second dielectric layer includes a dielectric material having a modulus of elasticity less than 3.5 Giga-Pascal (GPa), a dielectric constant less than 2.7, a dielectric loss less than 0.002, a breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), a temperature stability to 3000 Celsius, a defect densities less than 0.5/centimeter, a pinhole free in films greater than 50 Angstroms, and is capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 10%.


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