The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2014

Filed:

Jan. 18, 2013
Applicant:

Broadcom Corporation, Irvine, CA (US);

Inventors:

Weimin Feng, Suwanee, GA (US);

Paul McGlynn, Roswell, GA (US);

David Lwin, San Dimas, CA (US);

David Erickson, San Clemente, CA (US);

Haisong Wang, Fremont, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 7/16 (2011.01); H04N 21/61 (2011.01); H04N 21/434 (2011.01); H04N 21/41 (2011.01); H04N 21/643 (2011.01); H04N 21/426 (2011.01); H04N 21/6437 (2011.01); H04L 12/28 (2006.01);
U.S. Cl.
CPC ...
H04N 21/41 (2013.01); H04N 21/6118 (2013.01); H04N 21/434 (2013.01); H04N 21/6175 (2013.01); H04N 21/64322 (2013.01); H04N 21/4263 (2013.01); H04N 21/6437 (2013.01); H04N 21/6168 (2013.01); H04N 7/165 (2013.01); H04N 21/42676 (2013.01); H04N 21/42615 (2013.01); H04L 12/2801 (2013.01);
Abstract

A processor for a cable television set-top box has an interface for coupling the processor to a second processor. The processor also has a port that is coupleable to control a tuner, a demodulator and a DOCSIS module with or without DSG support. The tuner has an output coupled to the demodulator input, and the demodulator has an output to the DOCSIS module input. The demodulator's output is also coupled to a conditional access module controlled by the second processor. The processor issues commands via the port to control at least one of the tuner and the demodulator based on instructions received via the interface from the second processor.


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