The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2014

Filed:

Apr. 20, 2012
Applicants:

Adrian C. Gerhard, Rochester, MN (US);

Lyle E. Grosbach, Rochester, MN (US);

Daniel F. Moertl, Rochester, MN (US);

Inventors:

Adrian C. Gerhard, Rochester, MN (US);

Lyle E. Grosbach, Rochester, MN (US);

Daniel F. Moertl, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 3/06 (2006.01); G06F 13/12 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 3/0659 (2013.01); G06F 3/061 (2013.01); G06F 13/126 (2013.01);
Abstract

A method and controller for implementing storage adapter performance optimization with chained hardware operations completion coalescence, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines, and a processor. A plurality of the command blocks are selectively arranged by firmware in a predefined chain including a plurality of simultaneous command blocks. All of the simultaneous command blocks are completed in any order by respective hardware engines, then the next command block in the predefined chain is started under hardware control without any hardware-firmware (HW-FW) interlocking with the simultaneous command block completion coalescence.


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