The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2014
Filed:
Mar. 01, 2012
Jason N. Dale, Austin, TX (US);
Miles R. Dooley, Austin, TX (US);
Richard J. Eickemeyer, Rochester, MN (US);
Bradly G. Frey, Austin, TX (US);
Yaoqing Gao, North York, CA;
Francis P. O'connell, Austin, TX (US);
Jeffrey A. Stuecheli, Austin, TX (US);
Jason N. Dale, Austin, TX (US);
Miles R. Dooley, Austin, TX (US);
Richard J. Eickemeyer, Rochester, MN (US);
Bradly G. Frey, Austin, TX (US);
Yaoqing Gao, North York, CA;
Francis P. O'Connell, Austin, TX (US);
Jeffrey A. Stuecheli, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A prefetch unit includes a transience register and a length register. The transience register hosts an indication of transient for data stream prefetching. The length register hosts an indication of a stream length for data stream prefetching. The prefetch unit monitors the transience register and the length register. The prefetch unit generates prefetch requests of data streams with a transient property up to the stream length limit when the transience register indicates transient and the length register indicates the stream length limit for data stream prefetching. A cache controller coupled with the prefetch unit implements a cache replacement policy and cache coherence protocols. The cache controller writes data supplied from memory responsive to the prefetch requests into cache with an indication of transient. The cache controller victimizes cache lines with an indication of transient independent of the cache replacement policy.