The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2014
Filed:
Feb. 22, 2012
Applicant:
Deepak Jindal, Noida, IN;
Inventor:
Deepak Jindal, Noida, IN;
Assignee:
Freescale Semiconductor, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 19/00 (2011.01); G01R 31/3185 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G05B 1/00 (2006.01); G01R 31/3163 (2006.01); G01R 31/30 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G05B 1/00 (2013.01); G01R 31/318575 (2013.01); G01R 31/318577 (2013.01); G01R 31/31721 (2013.01); G01R 31/3177 (2013.01); G01R 31/28 (2013.01); G01R 31/3163 (2013.01); G01R 31/318536 (2013.01); G01R 31/30 (2013.01);
Abstract
A system for testing electronic circuits includes first, second, and third standard interfaces. A test port master and a test port slave are connected to an external testing apparatus. The first, second, and third standard interfaces are tested in first, second, and third test modes, respectively. The tests are initiated by asserting a test mode activate and first, second, and third test mode enable signals, respectively, which enable reuse of test patterns across different electronic circuits.