The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2014

Filed:

Jul. 22, 2010
Applicant:

Yoshimitsu Yamauchi, Osaka, JP;

Inventor:

Yoshimitsu Yamauchi, Osaka, JP;

Assignee:

Sharp Kabushiki Kaisha, Osaka-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/00 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3648 (2013.01); G09G 2300/0814 (2013.01); G09G 3/3659 (2013.01); G09G 2300/0809 (2013.01); G09G 3/3655 (2013.01); G09G 2300/0465 (2013.01); G09G 2300/0876 (2013.01); G09G 3/3614 (2013.01); G09G 2330/021 (2013.01); G09G 2320/0247 (2013.01); G09G 2300/0417 (2013.01);
Abstract

In a display device including a pixel circuit having a transistor with a low electron mobility, low power consumption is realized without decreasing an aperture ratio. An liquid crystal capacitor element (Clc) is formed between a pixel circuit () and a counter electrode (). One ends of the pixel electrode (), a first switch circuit (), and a second switch circuit () and a first terminal of a second transistor (T) form an internal node (N). The other end of the first switch circuit () is connected to a source line (SL). The second switch circuit () has the other end connected to a voltage supply line (VSL), and is a series circuit of transistors (Tand T). A control terminal of the transistor (T), a second terminal of the transistor (T), and one end of the boost capacitor element (Cbst) form an output node (N). The other end of the boost capacitor element (Cbst) and the control terminal of the transistor (T) are connected to a selecting line (SEL) and a reference line REF, respectively. A control terminal of the transistor (T) is connected to the selecting line (SEL) through a delay circuit ().


Find Patent Forward Citations

Loading…