The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2014

Filed:

Jan. 21, 2011
Applicants:

Jeongsik Yang, Cupertino, CA (US);

Chan Hong Park, San Jose, CA (US);

Sang-oh Lee, Cupertino, CA (US);

Inventors:

Jeongsik Yang, Cupertino, CA (US);

Chan Hong Park, San Jose, CA (US);

Sang-oh Lee, Cupertino, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/16 (2006.01); H03D 7/14 (2006.01); H03D 7/16 (2006.01); H03L 7/081 (2006.01); H04L 27/36 (2006.01); H04L 27/38 (2006.01);
U.S. Cl.
CPC ...
H04L 27/3863 (2013.01); H03D 7/1441 (2013.01); H03D 7/165 (2013.01); H03D 7/1458 (2013.01); H03L 7/0812 (2013.01); H04L 27/368 (2013.01);
Abstract

System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal.


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