The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2014
Filed:
Sep. 20, 2011
David A. Grosch, Burlington, VT (US);
Marc D. Knox, Hinesburg, VT (US);
Erik A. Nelson, Waterbury, VT (US);
Brian C. Noble, Lagrangeville, NY (US);
David A. Grosch, Burlington, VT (US);
Marc D. Knox, Hinesburg, VT (US);
Erik A. Nelson, Waterbury, VT (US);
Brian C. Noble, Lagrangeville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails.