The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8853701 B1

Date of Patent:

Oct. 07, 2014

Filed:

Mar. 17, 2011

Semiconductor device, display device, and production method for semiconductor device and display device

Applicant:

Kazushige Hotta, Osaka, JP;

Inventor:

Kazushige Hotta, Osaka, JP;

Assignee:

Sharp Kabushiki Kaisha, Osaka, JP;

Attorney:

Chen Yoshimura LLP

Primary Examiner:

Laura Menz

Int. Cl.

CPC ...

H01L 21/00 (2006.01); H01L 21/8238 (2006.01); H01L 27/12 (2006.01); H01L 27/092 (2006.01); H01L 29/786 (2006.01);

U.S. Cl.

CPC ...

H01L 27/092 (2013.01); H01L 21/8238 (2013.01); H01L 27/1222 (2013.01); H01L 29/78696 (2013.01); H01L 27/1214 (2013.01);

Abstract

In order to efficiently manufacture a semiconductor device having a plurality of TFTs formed thereon, which can be applied to a variety of uses, a semiconductor device () is disclosed that is provided with a first P-type TFT (), a second P-type TFT (), a first N-type TFT (), and a second N-type TFT (), each having a channel region that is formed of polycrystalline silicon. When d1, d2, d3, and d4 respectively represent the concentrations of p-type impurities in the respective channel regions of the TFTs (to), at least three values out of d1, d2, d3, and d4 are mutually different, and d1, d2, d3, and d4 satisfy relations of d1<d2 and d3<d4.

Find Patent Forward Citations