The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2014

Filed:

Nov. 28, 2011
Applicants:

Woojin Kim, Yongin-si, KR;

Jangeun Lee, Suwon-si, KR;

Sechung OH, Suwon-si, KR;

Junho Jeong, Suwon-si, KR;

Heeju Shin, Yongin-si, KR;

Inventors:

Woojin Kim, Yongin-si, KR;

Jangeun Lee, Suwon-si, KR;

Sechung Oh, Suwon-si, KR;

Junho Jeong, Suwon-si, KR;

Heeju Shin, Yongin-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/22 (2006.01); C23C 16/46 (2006.01); C23C 16/40 (2006.01); H01L 43/10 (2006.01); C23C 16/455 (2006.01); C23C 16/34 (2006.01);
U.S. Cl.
CPC ...
C23C 16/345 (2013.01); H01L 27/222 (2013.01); C23C 16/46 (2013.01); C23C 16/403 (2013.01); H01L 43/10 (2013.01); C23C 16/45536 (2013.01);
Abstract

Provided is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device includes forming a plurality of magnetic memory patterns spaced apart from each other on a substrate, with each of the magnetic memory patterns including a free pattern, a tunnel barrier pattern, and a reference pattern which are stacked on the substrate, performing a magnetic thermal treatment process on the magnetic memory patterns, and forming a passivation layer on the magnetic memory patterns. The magnetic thermal treatment process and the forming of the passivation layer are simultaneously performed in one reactor.


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