The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2014

Filed:

Sep. 21, 2010
Applicants:

J. Bradley Chen, Los Gatos, CA (US);

Bennet S. Yee, Mountain View, CA (US);

David C. Sehr, Cupertino, CA (US);

Inventors:

J. Bradley Chen, Los Gatos, CA (US);

Bennet S. Yee, Mountain View, CA (US);

David C. Sehr, Cupertino, CA (US);

Assignee:

Google Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G06F 12/14 (2006.01); G06F 7/04 (2006.01); G06F 17/30 (2006.01); H04N 7/16 (2011.01); G06F 17/00 (2006.01); G06F 12/16 (2006.01); G06F 11/00 (2006.01); G08B 23/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus for executing untrusted application code are disclosed. An example apparatus includes an execution mode state indicator with a plurality of states. In the example apparatus, the execution mode state indicator is configured such that placing the execution mode state indicator in a first state causes the processor to operate in a first execution mode and placing the execution mode state indicator in a second state causes the processor to operate in a second execution mode. The example apparatus also includes an instruction processing module that is configured to implement a set of instructions in the first execution mode and designate one or more instructions of the set of instructions as illegal instructions in the second execution mode. The example apparatus further includes a memory system that, in the second execution mode, is configured to restrict access to a set of memory addresses accessible by the processor in the first execution mode to a subset of the set of memory addresses.


Find Patent Forward Citations

Loading…