The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2014

Filed:

Dec. 12, 2012
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, KR;

Inventor:

Hiroshi Sugawara, Yokohama, JP;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 7/00 (2006.01); H01L 21/66 (2006.01); G11C 29/00 (2006.01); G01R 31/27 (2006.01); G11C 29/08 (2006.01); G11C 29/12 (2006.01); G11C 29/26 (2006.01); G11C 5/04 (2006.01); G11C 16/00 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 22/00 (2013.01); G11C 29/006 (2013.01); G01R 31/275 (2013.01); G11C 5/02 (2013.01); G11C 5/025 (2013.01); G11C 5/06 (2013.01); G11C 29/08 (2013.01); G11C 5/04 (2013.01); H01L 22/32 (2013.01); G11C 16/00 (2013.01); G11C 16/0483 (2013.01); G11C 29/12005 (2013.01); G11C 29/26 (2013.01); G11C 2029/1206 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/49113 (2013.01);
Abstract

A plurality of master chips are arranged in a row on the wafer, each master chip including a power supply circuit providing a power supply voltage, and a plurality of slave chips are arranged in a column to at least one side of a corresponding master chip among the plurality of master chips, each slave chip including a memory cell array functionally operative in response to the power supply voltage provided by the corresponding master chip during wafer level testing.


Find Patent Forward Citations

Sugawara, Hiroshi. (2014). Fabrication and testing method for nonvolatile memory devices (U.S. Patent No. 8848472). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8848472

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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