The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2014

Filed:

Jun. 29, 2010
Applicants:

Chien-hsueh Chiang, Miao-Li County, TW;

Sz-hsiao Chen, Miao-Li County, TW;

Inventors:

Chien-Hsueh Chiang, Miao-Li County, TW;

Sz-Hsiao Chen, Miao-Li County, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G08C 19/16 (2006.01); G09G 3/32 (2006.01); G02F 1/1345 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3674 (2013.01); G09G 2330/02 (2013.01); G02F 1/13454 (2013.01); G02F 2202/103 (2013.01); G09G 2320/043 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0278 (2013.01); G09G 3/3677 (2013.01); G09G 2330/06 (2013.01); G09G 3/3266 (2013.01); G09G 2300/0408 (2013.01);
Abstract

A gate line driving module used on a liquid crystal display uses clock signal sources in replacement of a high level gate power source, such that the phenomenon of device characteristic drift occurring in the foregoing related art is avoided. The gate line driving module includes a plurality of odd-pixel gate line driving circuits, a plurality of even-pixel gate line driving circuits, and an auxiliary gate line driving circuit. A pair of neighboring odd-pixel gate line driving circuit and even-pixel gate line driving circuit exchange output signals thereof with each other in a forward or feedback manner for ensuring that each the odd-pixel gate line driving circuit and each the even-pixel gate line driving circuit are driven once. The auxiliary gate line driving circuit is used for ensuring that signal iteration of the gate line driving module is under normal operation.


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