The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2014

Filed:

Apr. 10, 2012
Applicants:

Michael K. Kerr, Johnson City, NY (US);

William F. Lawson, Vestal, NY (US);

Inventors:

Michael K. Kerr, Johnson City, NY (US);

William F. Lawson, Vestal, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 1/00 (2006.01); H03K 3/00 (2006.01); H03K 5/12 (2006.01); H03L 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and circuit for implementing protection for complementary metal oxide semiconductor (CMOS) output drivers, and a design structure on which the subject circuit resides are provided. An output driver stage transistor stack includes a plurality of series connected PFETs series connected with a plurality of series connected NFETs connected between upper and lower voltage supply rails. A pair of offset DC voltage levels provides respective gate voltages of an intermediate PFET and an intermediate NFET in the output driver stage transistor stack. A pair of pre-driver circuits receiving voltage level translated logic signals drive respective gate inputs of the upper PFET and the lower NFET in the output driver stage transistor stack. A voltage feedback circuit provides respective gate voltages of the PFET and NFET connected together in the output driver stage transistor stack.


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