The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2014

Filed:

Sep. 29, 2012
Applicant:

Integrated Device Technology, Inc., San Jose, CA (US);

Inventors:

Minhui Yan, San Jose, CA (US);

Chien-Chen Chen, San Jose, CA (US);

Harmeet Bhugra, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/094 (2006.01); H04L 25/02 (2006.01);
U.S. Cl.
CPC ...
H03K 19/09432 (2013.01); H04L 25/0272 (2013.01);
Abstract

Integrated circuit devices may utilize automatic methods for adjusting the tail currents of current mode logic (CML) cells, which compensate for variations in process corners and thereby enable reliable operation of high performance circuits, such as frequency synthesizers. An integrated circuit may include a current mode logic (CML) circuit responsive to at least one input signal and a variable current source electrically coupled to the CML circuit. This variable current source can be configured to sink (or source) a first current from (or to) the CML circuit in response to a control signal. A control circuit may also be provided, which is configured to generate the control signal in response to a process corner indication signal. This process corner indication signal, which may be generated by a process corner detection circuit, preferably has a magnitude that estimates a relative speed of a process corner associated with the integrated circuit device.


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