The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2014

Filed:

Aug. 01, 2012
Applicants:

Tae-young OH, Paju-Si, KR;

Heung-lyul Cho, Goyang-Si, KR;

Ji-eun Jung, Seoul, KR;

Inventors:

Tae-Young Oh, Paju-Si, KR;

Heung-Lyul Cho, Goyang-Si, KR;

Ji-Eun Jung, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/20 (2006.01); G02F 1/1368 (2006.01); G02F 1/1362 (2006.01); H01L 21/28 (2006.01); H01L 29/786 (2006.01); G02F 1/1333 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28008 (2013.01); H01L 27/1244 (2013.01); G02F 1/1368 (2013.01); G02F 1/136286 (2013.01); H01L 27/1288 (2013.01); G02F 2001/133357 (2013.01); H01L 27/1248 (2013.01); H01L 29/78636 (2013.01);
Abstract

A thin-film transistor array substrate and a fabrication method thereof according to an embodiment of the present invention are disclosed to form an interlayer insulating layer, thereby reducing a failure occurred during the process subsequent to a gate electrode. The thin-film transistor disclosed according to the present invention may include a substrate, a gate electrode formed on the substrate, a planarized insulating layer formed at a lateral surface portion of the gate electrode and at an upper portion of the substrate, a gate insulating layer formed on the planarized insulating layer containing an upper portion of the gate electrode, an active layer formed at an upper portion of the planarized insulating layer located at an upper side of the gate electrode, and a source electrode and a drain electrode formed on the active layer and separated from each other based on a channel region.


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