The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2014

Filed:

Feb. 21, 2012
Applicants:

Takeshi Suzuki, Osaka, JP;

Koichi Hirano, Osaka, JP;

Shinobu Masuda, Osaka, JP;

Inventors:

Takeshi Suzuki, Osaka, JP;

Koichi Hirano, Osaka, JP;

Shinobu Masuda, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 21/027 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 33/08 (2010.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 29/786 (2013.01); H01L 21/0274 (2013.01); H01L 2223/54426 (2013.01); H01L 29/66742 (2013.01); H01L 27/124 (2013.01); H01L 29/78603 (2013.01); H01L 29/78606 (2013.01); H01L 33/08 (2013.01); H01L 23/544 (2013.01); H01L 2223/5442 (2013.01); H01L 29/78693 (2013.01);
Abstract

There is provided a method for manufacturing a flexible semiconductor device. The manufacturing method of the flexible semiconductor device of the present invention comprising the steps of: forming a gate electrode; forming a gate insulating film so that the gate insulating film contacts with the gate electrode; forming a semiconductor layer on the gate insulating film such that the semiconductor layer is opposed to the gate electrode; forming source and drain electrodes so that the source and drain electrodes contact with the semiconductor layer; forming a flexible film layer so that the flexible film layer covers the semiconductor layer and the source and drain electrodes; forming vias in the flexible film layer; forming a first metal layer by disposing a metal foil onto the flexible film layer, and thereby a semiconductor device precursor is provided; and subjecting the first metal layer to a processing treatment to form a wiring from a part of the first metal layer, wherein, in the step of the processing treatment of the first metal layer, the wiring is formed in a predetermined position by using at least one of the vias as an alignment marker.


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