The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2014
Filed:
Sep. 04, 2013
Applicant:
Fujitsu Semiconductor Limited, Yokohama, JP;
Inventor:
Masashi Shima, Yokohama, JP;
Assignee:
Fujitsu Semiconductor Limited, Yokohama, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/41 (2006.01); H01L 29/08 (2006.01); H01L 29/45 (2006.01); H01L 29/10 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66477 (2013.01); H01L 29/41 (2013.01); H01L 29/66659 (2013.01); H01L 29/0847 (2013.01); H01L 29/665 (2013.01); H01L 29/456 (2013.01); H01L 29/1045 (2013.01); H01L 29/7835 (2013.01); H01L 29/4933 (2013.01);
Abstract
A semiconductor device including a low-concentration impurity region formed on the drain side of an n-type MIS transistor, in a non-self-aligned manner with respect to an end portion of the gate electrode. A high-concentration impurity region is placed with a specific offset from the gate electrode and a sidewall insulating film. The semiconductor device enables the drain breakdown voltage to be sufficient and the on-resistance to decrease. A silicide layer is also formed on the surface of the gate electrode, thereby achieving gate resistance reduction and high frequency characteristics improvement.