The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2014
Filed:
Nov. 09, 2006
Applicants:
Iue-shuenn Chen, San Diego, CA (US);
Xuemin Chen, San Diego, CA (US);
Inventors:
Iue-Shuenn Chen, San Diego, CA (US);
Xuemin Chen, San Diego, CA (US);
Assignee:
Broadcom Corporation, Irvine, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/04 (2006.01); G06F 12/14 (2006.01); G06F 21/85 (2013.01); H04N 21/426 (2011.01); H04N 21/443 (2011.01); H04N 21/462 (2011.01); H04N 21/475 (2011.01); G06F 21/31 (2013.01);
U.S. Cl.
CPC ...
G06F 21/85 (2013.01); G06F 21/31 (2013.01); H04N 21/42623 (2013.01); H04N 21/42684 (2013.01); H04N 21/443 (2013.01); H04N 21/462 (2013.01); H04N 21/4753 (2013.01);
Abstract
Certain aspects of a method and system for allowing system-on-chip individual I/O control to be disabled and enabled by programmable non-volatile memory are disclosed. Aspects of one method may include mapping at least one bit of a control vector within a security processor comprising a non-volatile memory to each of a plurality of on-chip I/O physical buses. At least one of the plurality of on-chip I/O physical buses may be enabled or disabled by modifying the mapped bit or bits of the control vector.