The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2014
Filed:
Mar. 31, 2010
Indu Prathapan, Bangalore, IN;
Anjana Ghosh, Bangalore, IN;
Diganta Baishya, Bangalore, IN;
Sundarrajan Rangachari, Trichy, IN;
Sankar Prasad Debnath, Bangalore, IN;
Ranjit Kumar Dash, Chennai, IN;
Srinath Mathur Ramaswamy, Palakkad, IN;
Indu Prathapan, Bangalore, IN;
Anjana Ghosh, Bangalore, IN;
Diganta Baishya, Bangalore, IN;
Sundarrajan Rangachari, Trichy, IN;
Sankar Prasad Debnath, Bangalore, IN;
Ranjit Kumar Dash, Chennai, IN;
Srinath Mathur Ramaswamy, Palakkad, IN;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.