The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2014
Filed:
Mar. 28, 2012
Stefan Johansson, Round Rock, TX (US);
Keith E. Cheney, Austin, TX (US);
Patricia A. Abkowitz, Austin, TX (US);
Shardendu Pandey, Cedar Park, TX (US);
Gregory S. Hilton, Austin, TX (US);
Stefan Johansson, Round Rock, TX (US);
Keith E. Cheney, Austin, TX (US);
Patricia A. Abkowitz, Austin, TX (US);
Shardendu Pandey, Cedar Park, TX (US);
Gregory S. Hilton, Austin, TX (US);
Anue Systems, Inc., Austin, TX (US);
Abstract
Systems and methods are disclosed for modifying network packets to use unrecognized headers/fields for packet classification and forwarding in packet processing systems, such as network tool optimizer (NTO) devices. The packet modifications described allow standard switch or routing integrated circuits (ICs) to process, classify, and forward packets based upon data that is not typically recognized by the hardware capabilities of the standard packet routing circuitry for packet processing. Input packets are modified so that unrecognized data becomes recognized data for purposes of packet processing, classification, and forwarding by the packet routing circuitry. These modifications are then removed after packets are processed to reform the original packets. The original packets are then provided to destination devices based upon packet classification and forwarding control information. As such, packet processing, classification, and forwarding is provided in packet processing systems using headers/fields that are not supported for processing by standard switch or routing integrated circuits (ICs).