The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2014

Filed:

May. 27, 2013
Applicants:

Nitin Singh, Delhi, IN;

Amit Jindal, Sonipat, IN;

Anurag Jindal, Patiala, IN;

Inventors:

Nitin Singh, Delhi, IN;

Amit Jindal, Sonipat, IN;

Anurag Jindal, Patiala, IN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/289 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0375 (2013.01); H03K 3/0372 (2013.01);
Abstract

An integrated circuit (IC) includes a flip-flop that stores data when the IC is in built-in self-test (BIST) mode. The flip-flop includes a master latch connected to a slave latch, which in turn is connected to a data retention latch. A control circuit is connected to the flip-flop. During normal operation, the master latch receives a data input signal, which is transmitted through the slave latch to another flip-flop of the IC. When the control circuit initiates BIST (scan testing), data stored in the slave latch is transferred to the data retention latch. Upon completion of BIST, the data stored in the retention latch is used to restore the flip-flop to its original state.


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