The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2014
Filed:
Aug. 03, 2011
Yanxiang Liu, Wappingers Falls, NY (US);
Xiaodong Yang, Hopewell Junction, NY (US);
Gan Wang, Fishkill, NY (US);
Yanxiang Liu, Wappingers Falls, NY (US);
Xiaodong Yang, Hopewell Junction, NY (US);
Gan Wang, Fishkill, NY (US);
Globalfoundries, Inc., Grand Cayman, KY;
International Business Machines Corporation, Armonk, NY (US);
Abstract
CMOS devices (') having improved latch-up robustness are provided by including with one or both WELL regions () underlying the source-drains () and the body contacts (), one or more further regions (-) doped with deep acceptors or deep donors (or both) of the same conductivity type as the corresponding WELL region and whose ionization substantially increases as operating temperature increases. The increase in conductivity exhibited by these further regions as a result of the increasing ionization of the deep acceptors or donors off-sets, in whole or part, the temperature driven increase in gain of the parasitic NPN and/or PNP bipolar transistors inherent in prior art CMOS structures. By clamping or lowering the gain of the parasitic bipolar transistors, the CMOS devices (′) are less likely to go into latch-up with increasing operating temperature.