The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2014

Filed:

Sep. 11, 2012
Applicants:

Toshihiko Saito, Atsugi, JP;

Atsuo Isobe, Isehara, JP;

Kazuya Hanaoka, Fujisawa, JP;

Sho Nagamatsu, Isehara, JP;

Inventors:

Toshihiko Saito, Atsugi, JP;

Atsuo Isobe, Isehara, JP;

Kazuya Hanaoka, Fujisawa, JP;

Sho Nagamatsu, Isehara, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/76 (2006.01); H01L 27/108 (2006.01); H01L 29/04 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/04 (2013.01); H01L 27/1225 (2013.01); H01L 29/7869 (2013.01); H01L 29/78 (2013.01);
Abstract

A minute transistor and the method of manufacturing the minute transistor. A source electrode layer and a drain electrode layer are each formed in a corresponding opening formed in an insulating layer covering a semiconductor layer. The opening of the source electrode layer and the opening of the drain electrode layer are formed separately in two distinct steps. The source electrode layer and the drain electrode layer are formed by depositing a conductive layer over the insulating layer and in the openings, and subsequently removing the part located over the insulating layer by polishing. This manufacturing method allows for the source electrode later and the drain electrode layer to be formed close to each other and close to a channel forming region of the semiconductor layer. Such a structure leads to a transistor having high electrical characteristics and a high manufacturing yield even in the case of a minute structure.


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