The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2014
Filed:
Jul. 03, 2008
Hyung Hwan Kim, Gyeonggi-do, KR;
Kwang Kee Chae, Gyeonggi-do, KR;
Jong Goo Jung, Gyeonggi-do, KR;
OK Min Moon, Gyeonggi-do, KR;
Young Bang Lee, Gyeonggi-do, KR;
Sung Eun Park, Seoul, KR;
Hyung Hwan Kim, Gyeonggi-do, KR;
Kwang Kee Chae, Gyeonggi-do, KR;
Jong Goo Jung, Gyeonggi-do, KR;
Ok Min Moon, Gyeonggi-do, KR;
Young Bang Lee, Gyeonggi-do, KR;
Sung Eun Park, Seoul, KR;
Hynix Semiconductor Inc., Kyoungki-do, KR;
Abstract
An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.