The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2014

Filed:

Jun. 12, 2013
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Hyung Sup Yoon, Daejeon, KR;

Byoung-Gue Min, Daejeon, KR;

Jong-Won Lim, Daejeon, KR;

Ho Kyun Ahn, Daejeon, KR;

Jong Min Lee, Daejeon, KR;

Seong-il Kim, Daejeon, KR;

Jae Kyoung Mun, Daejeon, KR;

Eun Soo Nam, Daejeon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28008 (2013.01);
Abstract

Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced. The method of manufacturing a field effect type compound semiconductor device includes: stacking an active layer and an ohmic layer on a substrate and forming a first oxide layer on the ohmic layer; forming a mesa region in predetermined regions of the first oxide layer, the ohmic layer, and the active layer; planarizing the mesa region after forming a nitride layer by evaporating a nitride on the mesa region; forming an ohmic electrode on the first oxide layer; forming a minute gate resist pattern after forming a second oxide layer on a semiconductor substrate in which the ohmic electrode is formed and forming a minute gate pattern having a under-cut shaped profile by dry-etching the first oxide layer, the nitride layer, and the second oxide layer; forming a gate recess region by forming a head pattern of a gamma gate electrode on the semiconductor substrate; and forming the gamma gate electrode by evaporating refractory metal on the semiconductor substrate in which the gate recess region is formed.


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