The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2014

Filed:

Sep. 30, 2011
Applicants:

Ramaswamy Sivaramakrishnan, San Jose, CA (US);

Ali Vahidsafa, Palo Alto, CA (US);

Aaron S. Wynn, San Jose, CA (US);

Connie W. Cheung, Sunnyvale, CA (US);

Inventors:

Ramaswamy Sivaramakrishnan, San Jose, CA (US);

Ali Vahidsafa, Palo Alto, CA (US);

Aaron S. Wynn, San Jose, CA (US);

Connie W. Cheung, Sunnyvale, CA (US);

Assignee:

Oracle International Corporation, Redwood City, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/16 (2006.01); G06F 12/12 (2006.01); G06F 9/30 (2006.01); G06F 12/08 (2006.01); G06F 11/20 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1666 (2013.01); G06F 12/0844 (2013.01); G06F 2212/1008 (2013.01); G06F 12/0804 (2013.01); G06F 11/20 (2013.01); G06F 12/126 (2013.01); G06F 9/30 (2013.01);
Abstract

The systems and methods described herein may provide a flush-retire instruction for retiring 'bad' cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.


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