The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2014
Filed:
Feb. 15, 2011
Valeria Mihalache, Santa Clara, CA (US);
Hem C. Neema, Sunnyvale, CA (US);
Kumar Deepak, San Jose, CA (US);
Sonal Santan, San Jose, CA (US);
Valeria Mihalache, Santa Clara, CA (US);
Hem C. Neema, Sunnyvale, CA (US);
Kumar Deepak, San Jose, CA (US);
Sonal Santan, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
In one embodiment, a method is provided for generating dataflow-driven simulation code of a circuit design described with a combination of first and second HDLs. The circuit description is elaborated and a simulation dataflow graph of the circuit description is generated. Simulation code, configured to model execution of the design in a data-driven manner according to the simulation dataflow graph, is generated from the dataflow graph using a first HDL signal representation having a format compatible with the first HDL and a second HDL signal representation having a format compatible with the second HDL. For each instantiated module of the circuit description at a cross language boundary in the simulation dataflow graph, ports of the instantiated module are mapped to the first HDL signal representation and mapped to the second HDL signal representation.