The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2014

Filed:

Aug. 02, 2013
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Yanjing Ke, Union City, CA (US);

Thungoc M Tran, San Jose, CA (US);

Weiqi Ding, Fremont, CA (US);

Jie Shen, Fremont, CA (US);

Xiong Liu, Cupertino, CA (US);

Sangeeta Raman, San Jose, CA (US);

Peng Li, Palo Alto, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/159 (2006.01); H04L 27/01 (2006.01);
U.S. Cl.
CPC ...
H04L 27/01 (2013.01);
Abstract

One embodiment relates to a receiver with both decision feedback equalization and on-die instrumentation. A clock data recovery loop obtains a recovered clock signal from an input signal, and a first sampler, which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.


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