The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2014
Filed:
Jul. 23, 2013
Applicant:
Cypress Semiconductor Corporation, San Jose, CA (US);
Inventors:
Ravlndra Kapre, San Jose, CA (US);
Shahin Sharifzadeh, Menlo Park, CA (US);
Assignee:
Cypress Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/02 (2006.01); H01L 27/092 (2006.01); H02H 9/02 (2006.01); G11C 11/417 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 11/417 (2013.01); H01L 27/0921 (2013.01); H02H 9/025 (2013.01); G11C 5/14 (2013.01);
Abstract
A current-limiting device may be configured to be placed along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the power bus.
Kapre, Ravlndra. (2014). Memory cell array latchup prevention (U.S. Patent No. 8837245). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8837245
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile