The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2014

Filed:

Aug. 31, 2012
Applicants:

Wataru Sakamoto, Yokkaichi, JP;

Fumitaka Arai, Yokkaichi, JP;

Takashi Kobayashi, Yokkaichi, JP;

Ken Komiya, Yokkaichi, JP;

Shinichi Sotome, Yokkaichi, JP;

Tatsuya Kato, Yokkaichi, JP;

Inventors:

Wataru Sakamoto, Yokkaichi, JP;

Fumitaka Arai, Yokkaichi, JP;

Takashi Kobayashi, Yokkaichi, JP;

Ken Komiya, Yokkaichi, JP;

Shinichi Sotome, Yokkaichi, JP;

Tatsuya Kato, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01); H01L 21/28 (2006.01); H01L 29/788 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/04 (2013.01); G11C 16/0483 (2013.01); G11C 16/3459 (2013.01); G11C 16/10 (2013.01); G11C 11/5628 (2013.01); H01L 21/28273 (2013.01); H01L 29/788 (2013.01);
Abstract

A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written.


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