The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2014

Filed:

Nov. 19, 2010
Applicant:

Yoshimitsu Yamauchi, Osaka, JP;

Inventor:

Yoshimitsu Yamauchi, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/00 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3648 (2013.01); G09G 3/3659 (2013.01); G09G 2300/0819 (2013.01); G09G 3/36 (2013.01); G09G 3/3614 (2013.01); G09G 2300/043 (2013.01); G09G 3/3655 (2013.01); G09G 2320/0247 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); G09G 2300/0814 (2013.01); G09G 3/3618 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0465 (2013.01); G09G 2300/0876 (2013.01); G09G 2320/043 (2013.01);
Abstract

A display device which can prevent deterioration of a liquid crystal and reduction in display quality at low power consumption without lowering an aperture ratio is provided. An opposite voltage (Vcom) is applied to an opposite electrode () of a liquid crystal capacitive element (Clc). One ends of a pixel electrode (), a first switch circuit (), a second switch circuit (), and a first terminal of a second transistor (T) form an internal node (N). The other ends of the first switch circuit () and the second switch circuit () are connected to a source line (SL) and a voltage supply line (VSL), respectively. A control terminal of a first transistor (T) in the second switch circuit (), a second terminal of the second transistor (T), and one end of a boost capacitive element (Cbst) form an output node (N). The other end of the boost capacitive element (Cbst) and the control terminal of the second transistor (T) are connected to a boost line (BST) and a reference line (REF), respectively. This configuration makes it possible to perform an action (self-refresh action) to return the absolute value of the voltage between both ends of a display element part to the value at the time of a last writing action without performing a writing action.


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