The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2014

Filed:

Sep. 12, 2012
Applicant:

Tadamasa Murakami, Yokohama, JP;

Inventor:

Tadamasa Murakami, Yokohama, JP;

Assignee:

Samsung Electro-Mechanics Co., Ltd., Suwon, Gyunggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/16 (2006.01); H03K 19/0948 (2006.01); H01L 27/12 (2006.01); H03F 1/52 (2006.01); H01L 29/78 (2006.01); H03F 3/193 (2006.01); H01L 21/761 (2006.01); H01L 27/092 (2006.01); H01L 27/13 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 27/0629 (2013.01); H03K 19/0948 (2013.01); H01L 27/1203 (2013.01); H03F 2200/294 (2013.01); H03F 1/523 (2013.01); H01L 29/78 (2013.01); H03F 3/193 (2013.01); H01L 21/761 (2013.01); H01L 27/13 (2013.01); H03F 2200/492 (2013.01);
Abstract

There is provided a CMOS integrated circuit capable of avoiding deterioration of NF characteristic and achieving a high degree of linearity in the case in which an LNA circuit is formed on an SOI substrate and an LAN circuit is formed in a bulk CMOS process. The CMOS integrated circuit includes a field effect transistor having a gate electrode connected to a signal input terminal, a drain electrode connected to a power terminal, and a source electrode connected to a ground terminal, wherein the field effect transistor is formed on the SOI substrate and a connection between a body potential and a potential lower than a source potential are formed by a resistor element. The deterioration of NF characteristic can be avoided and a high degree of linearity can be achieved by using this CMOS integrated circuit.


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