The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8836387 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 16, 2014

Filed:

Jan. 04, 2011
Applicants:

Jin Xie, Longmont, CO (US);

Bin NI, Sunnyvale, CA (US);

Mats Oberg, Cupertino, CA (US);

Inventors:

Jin Xie, Longmont, CO (US);

Bin Ni, Sunnyvale, CA (US);

Mats Oberg, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and systems for compensating reducing jitter produced by a phase-locked loop are disclosed. For example, in a particular embodiment, a phase-locked loop device for reducing jitter may include a voltage-control oscillator (VCO) signal configured to produce a VCO signal, phase-detection circuitry configured to compare an input signal and the VCO signal to produce a phase error signal, and slew-rate limiting circuitry configured to receive the phase error signal and apply a slew-rate limit process on the phase error signal to produce a modified error signal.


Find Patent Forward Citations

Xie, Jin. (2014). Methods and systems for reducing jitter (U.S. Patent No. 8836387). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8836387

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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