The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2014
Filed:
Dec. 21, 2011
Hadi Parandeh Afshar, Chavannes-pres-renens, CH;
David Novo Bruña, Lausanne, CH;
Paolo Ienne Lopez, Pully, CH;
Hadi Parandeh Afshar, Chavannes-pres-renens, CH;
David Novo Bruña, Lausanne, CH;
Paolo Ienne Lopez, Pully, CH;
Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, CH;
Abstract
New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is an AND-Inverter Cone (AIC), which is a binary tree including one or more AND gates with a programmable conditional inversion and a number of intermediary outputs. Compared to LUTs, AICs are richer in terms of input and output bandwidth, because the area of the AICs grows only linearly with the number of inputs. Also, the delay grows only logarithmically with the input count. The new logic blocks can map circuits more efficiently than LUTs, because the AICs are multi-output blocks and can cover more logic depth due to the higher input bandwidth.