The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2014
Filed:
Jan. 30, 2012
Ki-young Yun, Suwon-si, KR;
Yeong-lyeol Park, Yongin-si, KR;
Ki-soon Bae, Yongin-si, KR;
Woon-seob Lee, Suwon-si, KR;
Sung-dong Cho, Hwaseong-si, KR;
Sin-woo Kang, Suwon-si, KR;
Sang-wook Ji, Seoul, KR;
Eun-ji Kim, Seoul, KR;
Ki-Young Yun, Suwon-si, KR;
Yeong-Lyeol Park, Yongin-si, KR;
Ki-Soon Bae, Yongin-si, KR;
Woon-Seob Lee, Suwon-si, KR;
Sung-Dong Cho, Hwaseong-si, KR;
Sin-Woo Kang, Suwon-si, KR;
Sang-Wook Ji, Seoul, KR;
Eun-Ji Kim, Seoul, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A semiconductor device includes a substrate having a via region and a circuit region, an insulation interlayer formed on a top surface of the substrate, a through electrode having a first surface and a second surface, wherein the through electrode penetrates the via region of the substrate and the second surface is substantially coplanar with a bottom surface of the substrate, a first upper wiring formed on a portion of the first surface of the through electrode, a plurality of via contacts formed on a portion of a top surface of the first upper wiring, and a second upper wiring formed on the plurality of via contacts.