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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8832843 B1

PDFFull Text
Date of Patent:
Sep. 09, 2014

Filed:

May. 20, 2010

Storage devices with secure debugging capability and methods of operating the same

Applicant:

Chanho Yoon, Seoul, KR;

Inventor:

Chanho Yoon, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., , KR;

Attorney:

Myers Bigel Sibley & Sajovec, P.A.

Primary Examiner:

Jeffrey Pwu

Assistant Examiner:

Jayesh Jhaveri

Int. Cl.
CPC ...
G06F 7/04 (2006.01); G06F 17/30 (2006.01); H04N 7/16 (2011.01); G06F 11/30 (2006.01); G06F 11/36 (2006.01); G06F 21/78 (2013.01); H04L 9/32 (2006.01); G06F 11/00 (2006.01); G06F 21/00 (2013.01); G06F 13/36 (2006.01); G06F 9/00 (2006.01); H04L 29/06 (2006.01);
U.S. Cl.
CPC ...
G06F 11/362 (2013.01); H04L 9/32 (2013.01); G06F 11/3089 (2013.01); G06F 11/30 (2013.01); G06F 11/00 (2013.01); G06F 21/00 (2013.01); G06F 13/36 (2013.01); G06F 21/78 (2013.01); G06F 11/3648 (2013.01); G06F 9/00 (2013.01); H04L 63/00 (2013.01);
Abstract

A device includes a first bus, a second bus, a processor configured to communicate with a storage circuit through the first bus and to communicate with a debug host through the second bus and a control circuit configured to inhibit transfer of data from the second bus to the debug host while receiving authentication information from the debug host and to enable transfer of data from the second bus to the debug host responsive to authentication of the received authentication information. The control circuit may be configured to inhibit data transfer from the second bus to the debug host by causing dummy data to be transmitted to the debug host over a transmit channel between the device and the debug host.

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