The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Feb. 28, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jae-Hoon Jeong, Hwaseong-si, KR;

Chang-Woo Ko, Seoul, KR;

Ki-Jae Song, Paju-si, KR;

Hun-Kyo Seo, Chungcheongnam-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G01R 1/04 (2006.01); G01R 31/28 (2006.01); G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
G01R 1/0408 (2013.01); G01R 31/2808 (2013.01); G06F 17/5068 (2013.01); G11C 2029/5602 (2013.01); G11C 29/56 (2013.01);
Abstract

In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.


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Jeong, Jae-Hoon. (2014). Package test devices having a printed circuit board (U.S. Patent No. 8832638). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8832638

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