The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2014
Filed:
Mar. 14, 2013
Coventor, Inc., Cary, NC (US);
David M. Fried, South Salem, NY (US);
Kenneth B. Greiner, Arlington, MA (US);
Mark J. Stock, Newton Center, MA (US);
Stephen R. Breit, Wayland, MA (US);
Coventor, Inc., Cary, NC (US);
Abstract
A virtual fabrication environment that enables 3D Design Rule Checks (DRCs) or Optical Rule Checks (ORCs) on 3D structural models of semiconductor devices to be performed is discussed. The virtual fabrication environment may perform 3D design rule checks, such as minimum line width, minimum space between features, and minimum contact area between adjacent materials, directly in 3D without making assumptions about the translation from 2D design data to a 3D structure effected by an integrated process flow for semiconductor devices. The required number of 3D design rule checks may therefore be significantly reduced from the number of design rule checks required in 2D environments. Embodiments may also perform the 3D design rule checks for a range of statistical variations in process and design parameters.