The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Nov. 18, 2010
Applicants:

Carson Henrion, Ft. Collins, CO (US);

Michael Dreesen, Timnath, CO (US);

Inventors:

Carson Henrion, Ft. Collins, CO (US);

Michael Dreesen, Timnath, CO (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/04 (2006.01); G11C 7/10 (2006.01); G11C 29/26 (2006.01); G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1069 (2013.01); G11C 29/56 (2013.01); G11C 7/1096 (2013.01); G11C 29/26 (2013.01); G11C 2029/2602 (2013.01); G11C 2029/0401 (2013.01);
Abstract

Apparatus and methods are provided for concurrently selecting multiple arrays of memory cells when accessing a memory element. A memory element includes a first array of one or more memory cells coupled to a first bit line node, a second array of one or more memory cells coupled to a second bit line node, access circuitry for accessing a first memory cell in the first array, a first transistor coupled between the first bit line node and the access circuitry, and a second transistor coupled between the second bit line node and the access circuitry. A controller is coupled to the first transistor and the second transistor, and the controller is configured to concurrently activate the first transistor and the second transistor to access the first memory cell in the first array.


Find Patent Forward Citations

Loading…