The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Apr. 01, 2013
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Alexander Branover, Chestnut Hill, MA (US);

Norman M. Hack, Pflugerville, TX (US);

Maurice B. Steinman, Marlborough, MA (US);

John Kalamatianos, Arlington, MA (US);

Jonathan M. Owen, Northborough, MA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/32 (2006.01); G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3275 (2013.01); Y02B 60/1225 (2013.01); Y02B 60/1217 (2013.01); G06F 12/0864 (2013.01); G06F 1/3296 (2013.01); G06F 1/324 (2013.01); G06F 1/3203 (2013.01); Y02B 60/1285 (2013.01); G06F 2212/1028 (2013.01);
Abstract

A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.


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