System-on-chip with power-save mode processor

Abstract

A system-on-chip (SoC) is provided with a low power processor to manage power-save mode operations. The SoC has a high-speed group with a high-speed processor, a standby agent, and a governor. In response to inactivity, the governor establishes a power-save mode and deactivates the high-speed group, but not the standby agent. The standby agent monitors SoC input/output (IO) interfaces, and determines the speed requirements associated with a received communication. In response to determining that the communication does not prompt a high-speed SoC operation, the standby agent responds to the communication. Likewise, the standby agent monitors SoC internal events such as housekeeping and timer activity, and the standby performs the tasks if it is determined that the tasks do not require a high-speed SoC operation. Alternatively, if monitored communication or internal event prompts a high-speed SoC operation, the governor activates a member of the high-speed group.