The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2014
Filed:
Oct. 30, 2007
Applicants:
Hagop Nazarian, San Jose, CA (US);
Ali Pourkeramati, Hills, CA (US);
Inventors:
Hagop Nazarian, San Jose, CA (US);
Ali Pourkeramati, Hills, CA (US);
Assignee:
Spansion LLC, Sunnyvale, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 16/08 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5621 (2013.01); G11C 16/08 (2013.01); G11C 2211/5641 (2013.01);
Abstract
A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode.
Quick Actions:
Nazarian, Hagop. (2014). Non-volatile memory array partitioning architecture and method to utilize single level cells and multi-level cells within the same memory (U.S. Patent No. 8832408). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8832408
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile