The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Apr. 04, 2011
Applicants:

Go Uehara, Odawara, JP;

Koji Sonoda, Chigasaki, JP;

Junji Ogawa, Sagamihara, JP;

Inventors:

Go Uehara, Odawara, JP;

Koji Sonoda, Chigasaki, JP;

Junji Ogawa, Sagamihara, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 11/10 (2006.01); G06F 12/02 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/064 (2013.01); G06F 11/108 (2013.01); G06F 11/1044 (2013.01); G06F 12/0246 (2013.01); G06F 2211/1059 (2013.01); G06F 3/0688 (2013.01); G06F 3/0616 (2013.01);
Abstract

A storage system having multiple flash memory packages including flash memory chips and package controllers for controlling access to the flash memory chips is configured such that the package controller receives from a higher-level apparatus, which sends a write request, frequency prediction information that enables prediction of an update frequency with respect to data, which is to be a write target, and when writing data for which a write request has been issued from the higher-level apparatus, control is executed such that data, which is predicted to have a relatively high update frequency based on the frequency prediction information, is preferentially stored in a physical block with the large remaining number of erases in a flash memory chip of flash memory package of the package controller, or such that data, which is predicted to have a relatively low update frequency based on the frequency prediction information, is preferentially stored in a physical block with the small remaining number of erases in a flash memory chip of the flash memory package of the package controller.


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