The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Mar. 16, 2007
Applicants:

Allen Chan, San Jose, CA (US);

Wilson Wong, San Francisco, CA (US);

Sergey Shumarayev, Los Altos Hills, CA (US);

Inventors:

Allen Chan, San Jose, CA (US);

Wilson Wong, San Francisco, CA (US);

Sergey Shumarayev, Los Altos Hills, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 27/00 (2006.01); H03K 19/177 (2006.01); G06F 13/38 (2006.01); H04L 5/14 (2006.01);
U.S. Cl.
CPC ...
G06F 13/385 (2013.01); H03K 19/17744 (2013.01); H03K 19/177 (2013.01); H04L 5/1446 (2013.01);
Abstract

Automatic rate negotiation logic for a high speed serial interface in a programmable logic device determines whether multiple occurrences of a single-bit transition (i.e., a data transition from '0' to '1' to “0” or from “1” to “0” to “1”) occur within a predetermined time interval on a data channel of a high-speed serial interface. The interval preferably is selected such that multiple occurrences of a single-bit transition mean that the data channel is operating in full-rate mode. The rate negotiation logic may share a phase detector with clock data recovery circuitry in the interface. The phase detector may be a bang-bang phase detector specially adapted to detect single-bit transitions.


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