The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2014
Filed:
Jul. 20, 2012
Applicants:
Jung Hyuk Lee, Yongin-si, KR;
Daewon Ha, Seoul, KR;
Kyu-rie Sim, Hwaseong-si, KR;
Inventors:
Assignee:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 8/00 (2006.01); G11C 29/02 (2006.01); G11C 13/00 (2006.01); G11C 17/16 (2006.01); G11C 11/16 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 8/00 (2013.01); G11C 2013/0076 (2013.01); G11C 13/0069 (2013.01); G11C 13/0007 (2013.01); G11C 17/16 (2013.01); G11C 29/021 (2013.01); G11C 13/0004 (2013.01); G11C 29/028 (2013.01); G11C 13/0038 (2013.01); G11C 2013/0092 (2013.01); G11C 11/16 (2013.01); G11C 2029/5006 (2013.01); G11C 2013/0083 (2013.01); G11C 13/00 (2013.01);
Abstract
A resistance change memory device includes an array of resistance change memory cells, and a writing circuit configured to reset a selected memory cell to a high resistance state by supplying a RESET current to the selected memory cell in the array of resistance change memory cells in a program operation mode, wherein a level of the RESET current depends on a distribution of initial RESET currents for the array of resistance change memory cells.
Quick Actions:
Lee, Jung. (2014). Resistance change memory device and current trimming method thereof (U.S. Patent No. 8830728). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8830728
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